2/14/2024 0 Comments Memory barrier cache coherenceIn ppc64 case, the atomic operation seems to be barriered trial loop. (In other words, the atomic operation of CPU1 causes implicit local-memory barrier effect to CPU2 reading? or not?) The problem here is whether the explicit barrier before the "CPU-2" reading is needed or not. (Recently, InnoDB on x86 x86_64 SMP seems not to hangup.) The barrier before the reading is not so needed by experience. (So, it should affect (or be affected) to CPU-2's prefetch/cache of the memory ordering (CPU-2 respects CPU-1 automatically?))Īt the time, if CPU-2 have to read the memory with consistency, The target memory (and cached value in all CPU) is locked or arbitrated actively. When CPU-1 does atomic operations using LOCK prefix, (memory barrier is not affect to the other CPU affect only ) I don't writing about memory barrier of atomic operation itself. I am writing about the interaction between processors. On PPC (probably on any non-Intel), I presume, one needs to add a memory barrier explicitly. ![]() What's different - on Intel in certain cases one needs to use LOCK prefix for an instruction to be really atomic, and LOCK prefix is an implicit full memory barrier. Accesses to the shared memory may need barriers. On on Intel the situation is the same - caches are coherent. And "sync" is just a glorified memory barrier (see p.532 in the "Programming Environment") which is important for mutexes, for example, (you want to be sure that all accesses to the mutex-protected memory are executed by the CPU *after* you locked the mutex and *before* you unlocked it). Synchronization instructions are different - that's for memory coherence between CPUs. Some go into details explaining bus snooping and the particular protocol. Check this one "970 User Manuals":įor example, it says explicitly "The 970FX automatically maintains the coherency of all data cached " all other PowerPC User Manuals say basically the same. Sergei Golubchik I think you read it incorrectly. Heavy benchmarking (using concurrent many sessions) on PowerPC SMP server. ![]() If it will need another patch to stabilize, I will upload the patch here. The following patch for InnoDB-Plugin 1.0.3 Otherwise, the wrong reading causes hangup of the mutex or rw_lock.Īnd the other variable or operation (writing?) may need synchronization also. So, reading unprotected (without mutex/rw_lock) shared memory needsĮxplicit syncronization before the reading. Specific protocols include the MSI protocol and its derivatives MESI, MOSI and MOESI.The Intel processors always maintain cache consistency automatically.Īll InnoDB code (both of builtin and Plugin, using atomic or not)ĭepends on the automatic consistency of Intel SMP.īut some other processors don't maintain cache consistency automatically.įor example, PowerPC need "Memory Synchronization Instructions" to respect When implemented in hardware, the coherency protocol can, for example, be directory-based or snooping-based (also called sniffing). In order to write correct concurrent programs, programmers must be aware of the exact consistency model that is employed by their systems. ![]() The exact nature and meaning of the memory coherency is determined by the consistency model that the coherence protocol implements. ![]() Consequently, some scheme is required to notify all the processing elements of changes to shared values such a scheme is known as a memory coherence protocol, and if such a protocol is employed the system is said to have a coherent memory. But as soon as one updates the location, the others might work on an out-of-date copy that, e.g., resides in their local cache. Provided none of them changes the data in this location, they can share it indefinitely and cache it as they please. As a result, when a value is changed, all subsequent read operations of the corresponding memory location will see the updated value, even if it is cached.Ĭonversely, in multiprocessor (or multicore) systems, there are two or more processing elements working at the same time, and so it is possible that they simultaneously access the same memory location. In a uniprocessor system (where there exists only one core), there is only one processing element doing all the work and therefore only one processing element that can read or write from/to a given memory location. Memory coherence is an issue that affects the design of computer systems in which two or more processors or cores share a common area of memory.
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